One example of a high speed digital circuit is a crosspoint switch, which can selectably connect data signals between multiple inputs and multiple outputs. FIG. 1 shows a slice of such a crosspoint switch showing a single path connecting one input port to one output port. The crosspoint switch can be conceptually divided into a high-speed data path (shown by thin lines in FIG. 1) and a lower-speed control plane that determines connectivity (shown by thick lines in FIG. 1). The control plane is run by a digital clocking signal and determines which pieces of the data path should be enabled for a given connectivity and when the enabling signals should change. For the switch control plane, connectivity data to control the data path may be written into control latches or flip-flops.
In FIG. 1, a first stage buffer 11 provides a high impedance input (with reduced input capacitance) and converts signal levels. Driving four sets of input lines from each of the second stage input buffers 12 reduces the number of point cells 13 loading each input by a factor of four. Groups of multiple point cells are provided to first stage multiplexers 14 to allow the associated data streams to be directed to a second stage multiplexer 15 driving a selected output port. The capacitance load on each point cell 13 is reduced by collecting multiple first stage multiplexers 14 for each second stage multiplexer 15. The second stage multiplexer 15 may also act as an output buffer.
However, circuits such as the crosspoint switch shown in FIG. 1 draw relatively high power and may have limited speed in a given process technology. To reduce power consumption, inactive circuit stages may be powered down or disabled and stages may be activated only when needed. This disabling tends to create uneven propagation delays through the path depending on when in a given cycle connectivity is updated. When an inactive stage is reactivated, the time it takes the stage to reach its enabled state increases the propagation delay through the data path. This increased propagation delay sets the largest delay condition and determines the maximum operating frequency of the data path.